1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and more particularly a microcomputer and a multi-chip module incorporating the same.
2. Description of the Prior Art
A growing number of connection terminals attached to semiconductor devices have been making it increasingly difficult to route the wiring properly for installing such a device onto a substrate. When mounted on a substrate of an enlarged scale, semiconductor devices are required to have a bus structure whose driving capacity should be large enough to transmit signals accurately throughout the substrate. These developments have been accompanied by extraneous radiation noise that requires suitable techniques for reduction. In addition, given the fact that test costs form an increasing proportion of overall semiconductor fabrication expenditures, there is a growing need for designs that facilitate testing procedures.
Some typical conventional examples relevant to the scope of this invention are described below.
FIG. 14 is a block diagram outlining the basic design of a circuit comprising a conventional microcomputer. In FIG. 14, reference numeral 1 stands for a printed-circuit board; 2 for a microcomputer comprising a ROM; 3 for an external memory; 4 and 5 for a first and a second peripheral circuit respectively; and 6 and 7 for a bus each. The external memory 3 is connected with the microcomputer 2 via the bus 6 interconnecting the circuit elements. The peripheral circuits 4 and 5 are connected with the microcomputer 2 via the bus 6 and are also connected to each other by way of the bus 7.
Upon access to the external memory 3, the microcomputer 2 transmits data and an address thereto over the bus 6. The microcomputer 2 also utilizes the bus 6 when controlling the peripheral circuits 4 and 5. The peripheral circuits 4 and 5 use the bus 7 for data exchanges therebetween.
FIG. 15 is a block diagram showing a typical configuration of the microcomputer 2. In FIG. 15, reference numeral 65 represents an output transistor group connected to the bus 6. The output transistor group 65 is activated when the microcomputer 2 either accesses the external memory 3 or controls the peripheral circuits 4 and 5. Here, it should be noted that the bus 6 connected to the external memory 3 has a large parasitic capacitance since it is also connected to the peripheral circuits 4 and 5. The need to drive that bus 6 at a high speed makes it impossible to reduce the driving capacity of the transistors constituting the output transistor group 65.
The first conventional example works as follows: a microcomputer terminal is selected to access the internal ROM functions as a normal port. In extended memory mode in which the microcomputer 2 gains access to the external memory 3, the bus functions as an address or data bus operating at a high speed. Illustratively, where the microcomputer 2 operates on a basic clock of 10 MHz, the external memory 3 is accessed in 100 ns. The microcomputer 2 accesses the internal ROM and, as needed according to the program contained therein, gains access to the peripheral circuits 4 and 5 via the terminal acting as the normal port also connected to the external memory 3. The speed at which to access the peripheral circuit 4 or 5 does not exceed the speed in accessing the external memory 3. If the second peripheral circuit 5 needs to be controlled both by the microcomputer 2 and by the first peripheral circuit 4, these circuit elements must be interconnected using suitable signals over the bus 7.
FIG. 16 is an explanatory view showing how a plane formed by a current loop forms an angle with respect to an observation point. In FIG. 16, reference numeral 62 stands for a closed circuit formed by a current, 63 for a plane constituted by the current circuit, and 64 for a power supply. According to Denshi Gijutsu ("Electronic Technology," a Japanese publication) 1996, Vol. 38, No. 5, the amount of radiation energy EM stemming from extraneous radiation noise is given by the expression (1) below: EQU E.sub.M =120{.sqroot. (.mu..sub.S /.epsilon..sub.S)}.pi..sup.2 IS(e.sup.-JKr /.lambda..sup.2 d)sin .theta.(V/m) (1)
where .mu..sub.S stands for relative magnetic permeability, .epsilon..sub.S for relative dielectric constant, I for the amount of current, S for the area occupied by the loop formed by current, Kr for propagation coefficient, .lambda. for wavelength, and .theta. for the angle between observation point and plane formed by current loop.
Because a plurality of circuit elements such as the peripheral circuits 4 and 5 and external memory 3 are connected to the bus 6, their wiring needs to be routed suitably over the printed-circuit board. Since the load capacitances of these circuit elements are parasitic on the wiring of the bus 6, the output transistor group 65 needs to have a driving capacity large enough to drive the bus 6 at high speed. However, the use of transistors with large driving capacities necessarily entails an increase in currents that flow through the wiring provided the impedance of external elements remains constant.
FIG. 17 is a graphic representation showing how time and voltage are related in comparing leading edges of output waveforms of transistors with different driving capacities. As illustrated in FIG. 17, a transistor with a large driving capacity generally produces an output waveform 71 with a steeper leading edge and a smaller wavelength .lambda. than a transistor with a small driving capacity yielding an output waveform 72. That is, as per the expression (1) above, transistors with large driving capacities are bound to have growing amounts of radiation energy E.sub.M stemming from extraneous radiation noise.
Although it is conceivable to use a buffer on the printed-circuit board to suppress currents so as to increase the driving capacity of the bus 6, the scheme has the disadvantage of increasing the number of parts used. In any case, the wiring tends to be elongated and parasitic capacities are raised, which makes it difficult to boost the speed of circuit operation. That is because wiring delay is generally proportionate to capacity and resistance involved. Furthermore, any of the conventional techniques above for enhancing the driving capacity of the output transistor group 65 entails an increased amount of currents. This promotes power dissipation and involves an increase in extraneous radiation.
In another conventional basic board design of circuits such as a circuit including the microcomputer in FIG. 14, it has become difficult to optimize the layout of the numerous circuit elements. One conventional solution to that bottleneck is the adoption of a multi-layer board concept at the basic design stage whereby signal lines are routed across layers. Another solution is to have peripheral elements mounted on the back of the board in a double-sided printed-circuit design.
FIGS. 18A and 18B show pin terminal arrangements of a conventional microcomputer 2' and of an external memory 3'. FIG. 18A is a pin terminal layout view of the external memory 3', and FIG. 18B is a pin terminal layout view of the microcomputer 2'. In the two figures, reference numerals 30a through 30h denote lines and pin terminals connecting the microcomputer 2' to the external memory 3' via the bus 6, the pins and lines being interconnected where they have the same reference numerals. Between the two layout views, the pin terminals 30a through 30h connecting the microcomputer 2' to the external memory 3' via the bus 6 do not match in sequence. The layout mismatch requires lines to be crossed on the board, which makes it impossible to route the wiring over the shortest possible distances.
In another conventional semiconductor integrated circuit design, the circuits inside a chip share common power supplies with the exception of special-purpose components (clock, analog power supply, etc.). FIG. 19 is a schematic view outlining power supply connections of a conventional microcomputer. In FIG. 19, reference numeral 2e stands for a microcomputer; 33' and 34' for a power supply line and a ground line respectively; 39' and 40' for a power supply pad and a ground pad respectively; 37b and 38b for a bus each; 37a for an output transistor group for driving the bus 37b connected to an external memory; and 38a for an output transistor group for driving the bus 38b connected to peripheral circuits.
The third conventional example works as follows: the power supply line 33' connected to the power supply pad 39' supplies power not only to the output transistor group 37a but also to the output transistor group 38a. The ground line 34' connected to the ground pad 40' feeds both output transistor groups 37a and 38a with ground potential. When transistors in the output transistor group 37a connected to the memory bus 37b are switched at high speed, the wavelength .lambda. in the expression (1) above is diminished. This oscillates the power supply line 33' at a high frequency of, say, 100 MHz, generating radiation noises inside the chip. Such radiation noise propagates through the other power supply line to reach other output pins which release the noises.
According to another conventional chip layout design, multi-chip module (MCM) technology allows a plurality of bare chips to be assembled into a single module that is small and lightweight. Because the multi-chip module has numerous wires, the inclusion in a single package of both a microcomputer and a memory subject to access at high frequency contributes to reducing the quantity of the wiring on the board. This setup, however, requires a general-purpose memory to be installed in the multi-chip module. The arrangement is costly for the manufacturer. It is thus desired to replace such a memory with an inexpensive built-in mask ROM of a single-chip microcomputer.
FIG. 20 is a block diagram of a conventional multi-chip module (MCM) constitution. In FIG. 20, reference numeral 53' stands for an MCM package; 54' for a microcomputer; 55 for an external memory; 101 for a normal port; 102 for a memory bus; 57 for a normal port input/output signal line group of the microcomputer 54'; and 58 for a memory bus signal line group of the microcomputer 54'. The memory bus signal line 58 is connected to the external memory 55 but, with no need to attach to any other component, is not connected to any external terminal of the MCM package 53'.
The microcomputer of FIGS. 14-17 configured as described above, is characterized by a large parasitic capacitance of the bus 6. That proves to be a major impediment to improving the access speed of the device as a whole. Attempts to boost the operating speed increase the amount of currents resulting in higher power dissipation in conjunction with the driving capacity of output transistors; extraneous radiation noise is also promoted.
The microcomputer of FIGS. 18A-18B configured as described above, has an elongated bus 6 extending from the microcomputer 2. This structure enlarges the area S of the loop formed by currents. According to the expression (1) above, the structure increases extraneous radiation noise. Because the wiring on the board is routed over long distances, the parasitic capacitance is increased along with signal delays, which keeps the speed of circuit operation low.
The microcomputer 2e of FIG. 19 configured as described above, has its output transistor groups 37a and 38a switched at high speed, generating radiation noise therebetween. The noise tends to propagate over the power supply line 33' and ground line 34.
The multi-chip module (MCM) configured as described above, has a microcomputer chip and a general-purpose memory chip simply wired on a multi-chip module board. Compared with the single-chip microcomputer setup, the example most often has disparate pin arrangements between the chip and the memory and are subject to worsening noise or power dissipation characteristics. This requires devising a complicated basic design.
The multi-chip module (MCM) of FIG. 20, configured as described above, has the memory bus signal line 58 connected only to the microcomputer 54' and external memory 55. Because the memory bus signal line 58 is not connected to any external terminal of the multi-chip module package, it is impossible to submit the external memory 55 to product inspection and failure analysis.
The microcomputer 54' thus needs to incorporate a circuit for evaluating the inspection and analysis functions in advance or is required to be programmed to let such evaluation be performed in a predetermined manner. These arrangements permit little degree of freedom in inspection and analysis procedures. Furthermore, it is necessary to develop anew test patterns by which to subject the multi-chip module 53' to product inspection. Such development takes time.